101 Old Blossom Hill Rd
Los Gatos, CA 95032-4856
To add value by overcoming engineering challenges.
|August, 2003 to present
- Successfully championed the use of development branches.
- Performed unit-level hardware design verification (testbed development, assertions, test cases, etc.)
- Re-engineered RTL build system using
Makepp, with a sandbox-based distributed build.
- Led Perforce server upgrade testing, and managed codebase metric data collection and reporting.
- Consulted locally on object orientation and design for verifiability.
- Supported and enhanced legacy infrastructure and ESL tools for hundreds of engineers.
- Developed and maintained code coverage tools for C++ hardware models.
- Performed MCM-level RTL build integration for G80.
|April, 2002 to August, 2003
DESIGN VERIFICATION MANAGER,
WIS Technologies (now Micronas)
- Automated nightly regression testing and coverage measurement.
- Re-engineered hierarchical synthesis makefiles.
- Administered Gnats bug tracking system. Led regular bug reviews.
- Installed and administered Perforce source control system.
- Managed third party software installations for Linux and Solaris.
|April, 1998 to September, 2001
SENIOR STAFF ENGINEER,
- Early employee of Maverick Networks, acquired May 31, 1999.
- Advocated and implemented smart-checker verification strategy for highly integrated
ethernet switch IC's.
- Implemented a high-level C++ performance model.
- Implemented register and memory database methodology.
- Wrote definitive functional specifications for all
Discovered dozens of behavioral
flaws in the product descriptions delivered by the architecture team.
- Designed and wrote tests, including comprehensive random tests,
and diagnosed over 450 confirmed bugs.
|August, 1993 to April, 1998
SENIOR CAD ENGINEER,
- Worked on cost-reduction shrinks. Implemented a methodology for generating
correct SPICE netlists based on original design schematics.
- Designed and maintained analog circuits, including voltage reference, charge pump,
PLL, DLL, I/O buffers and memories.
- Devised optimal sizing policy for the XC4000XLA FPGA family. Resulting cost
savings exceeded $10M.
- Maintained and enhanced all front-end IC design tools and cell libraries.
Used SKILL to develop various proprietary features.
- Wrote a SKILL program to add hierarchy to schematics.
- Created a correct-by-construction BSDL file generation methodology.
|July, 1990 to August, 1992
- Design and verification of RISC microprocessors.
|September, 1992 to June, 1993
MS/EE, Stanford University|
GPA: 4.2 of 4.3
|September, 1986 to June, 1990
GPA: 4.1 of 4.3
UNIX, Perl (guru), Makepp (developer), Perforce (guru),
C, C++, Object-oriented design, Verilog,
Vera, PLI, Opus SKILL, Java, Python, SPICE, Perl/Tk,
ePerl, RPC, HTML, Make, CVS, SCCS, RCS,
Photoshop, Visio, Assembly, Bourne & C shells, awk,
sed, vi, CPU-based system design.
PUBLICATIONS, HONORS & AWARDS
Contributions to GCC, Perl, CPAN & Makepp
||"Visualizing the Cost of Divergence ," 2009 Perforce User Conference|
||"'S' is for 'Source': The Role of the Build System in Configuration Management ," 2005 Perforce User Conference|
Engineering Philosophy Writings
||"Codeline Management for Evolutionary Development ," 2003 Perforce User Conference|
||"A Time-Multiplexed FPGA," FCCM '97|
|1992 to present
5,398,330 5,588,113 5,646,545 5,646,903 5,778,439
5,784,313 5,881,216 5,920,223 5,933,369 5,959,881
5,978,260 6,078,528 6,091,263 6,150,839 6,263,430
6,374,347 6,480,954 6,697,936 6,839,349
||S-MOS Outstanding Achievement Award|